Are you someone who steps up to challenges and thrives on group project work in a technology R&D environment?

As an ASIC Design Engineer – PDK/CAD Manager, you will build and maintain the design infrastructure, provide tool support and training, and serve as the custodial of the process design kits (PDKs) and CAD/EAD tools for our ASIC team. You will collaborate closely with other scientists, engineers, technicians and information technology experts on complex, meaningful projects for the Lab and our partners. Your role will be critical in enabling the development of high-performance analog, digital, and mixed-mode ASICs for scientific instruments. You will also be contributing to a broad range of low-noise, precision, mixed-signal ASIC designs that include radiation sensors front-ends, base-band analog, RF, digital, data converters, data transmission, photonic and artificial intelligence technologies.

Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high resolution X- and gamma-ray spectrometers, and high-rate photon counters and imagers. Our ASICs work in extreme environments (such as cryogenic temperatures) or must withstand extreme irradiation doses, thus represent unique layout challenges. We are also actively carrying out R&D programs focused on Quantum Information Science, Artificial Intelligence & Machine Learning, and Neuromorphic Processing that require ASICs with specific layouts. The applications of these ASICs extend beyond BNL to a variety of international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!

Essential Duties and Responsibilities:

• Build and maintain design environment to support operation of the ASIC development team at BNL through:

  • maintaining up-to-date organization of the pool of CAD/EDA ASIC design tools, PDKs, version-controlled repositories of design libraries, IP and outside-vendor libraries and their maintenance suitably for the current needs

  • working with the IT and security teams’ Linux-based cluster and its configuration for installation and maintenance of CAD/EDA design tools from major vendors, such as Cadence, Mentor, Synopsis,

  • integration of the designs in multi-user environment via process and design management tools, such as SOS Design Manager

  • organization of work directories, system shell scripts, tool scripts, physical and functional design verification decks, solutions for tools interoperability, procedures for efficient and secure organization of the design flows

  • set-up and maintenance of environments for Artificial Intelligence and Machine Learning modeling, simulations (such as PyTorch, TensorFlow and others) and integration with digital and mixed-mode IC design flows

  • set-up and maintenance of other ECAD tools supporting ASIC design efforts, such as physical-level device simulations, model extraction, calculus, and data presentation

• Interact with major vendors for providing optimized tools-set for the team; organize tools, process design kits, design techniques workshops and trainings, and introduction and monitoring of standardized design practices

• Participate in ASIC designs (analog, digital and mixed-mode, functional verification, etc.), upon qualifications and as necessary

Position Requirements:

Required Knowledge, Skills, and Abilities:

• Bachelor's degree in an engineering discipline or closely related field of study

• Minimum three (3) years related work experience

• Familiarity with specificity of ASIC design processes and flows

• Familiarity with PDKs and CAD/EDA tools for ASIC design and their interoperability

• Knowledge of operating system shell scripting or other scripting languages, such as Pearl, Python, and others

• Knowledge of SKILL, Tcl/Tk, ASSURA and Calibre DRC/LVS verification decks syntax 

Preferred Knowledge, Skills, and Abilities:

• Master’s degree in an engineering discipline or closely related field of study

• Ability to execute analog and/or digital ASIC design flows for performing design tasks

• Knowledge of back-end ASIC design elements, such as layout, physical verification, and design verification

• Ability to provide guidance in specific areas to the ASIC team

OTHER INFORMATION:

• The selected candidate will be placed at the appropriate level based on the depth and breadth of relevant engineering knowledge, skills and experience.

• This is an On-Site position.

Brookhaven National Laboratory is committed to providing fair, competitive, and market-informed compensation.This is a multi-level role and the full salary range for this position is $94250 - $155800 / year. Salary offers will be commensurate with the final candidate’s qualification and experience, including skills, knowledge, relevant education, and certifications, and also aligned with the internal peer group.